The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon, bipolar, and CMOS transistors and Galium Arsenide (GaAs) transistors, and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects, such as carrier tunneling through potential barriers. These effects led to development of alternative device structures which take advantage of such tunneling phenomenon; such as tunneling, and resonant tunneling, diodes and transistors. For ease of reference, all such structures are hereafter collectively referred to as tunneling diodes (TDs).
Tunneling diodes are generally two terminal devices with conduction carriers tunneling through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance (NDR) . This negative differential resistance characteristic may be used as the basis for a wide range of high performance designs.
Conventionally, tunneling and resonant tunneling diodes have been limited in implementation to GaAs and other high performance processes. Conventional methods focused on building TDs in GaAs for several reasons; mainly because the speed characteristics and small process features of GaAs processes were conducive to tunneling mechanics. Since GaAs and other such processes were not practical or cost efficient for high-volume, consumer-related production, TDs have generally been limited in application to research and developmental applications.
Previously, feature sizes of standard silicon processes, such as CMOS, were not conducive to producing such tunneling structures. In the absence of commercially viable TDs, conventional CMOS circuit designs have utilized functional components readily available in CMOS processes. Conventional methods have focused on optimizing the design of these components individually, and improving their efficiency when utilized within larger circuits. As such, conventional CMOS circuitry does not comprehend the use of, nor enjoy the performance and system overhead improvements provided by circuitry implemented with TDs.
As performance demands have increased and feature sizes for CMOS processes have decreased, fabrication of tunneling structures in a production CMOS process becomes feasible. Tunnel diode growth on silicon is relatively immature. Recently, CMOS compatible tunnel diodes have been demonstrated to show that a wide range of current densities can be obtained; addressing requirements for imbedded memory and signal processing applications.
For a very high speed A/D design, the architecture and each component thereof must be capable of very high bandwidth. In general, the simpler the circuitry--the faster it can operate (i.e. at a higher bandwidth) . This usually translates to designs that have as few nodes in the signal path as possible, and that utilize parallel paths for signal processing where possible. Additionally, use of components with inherently high bandwidth is required to achieve high speed performance desired.
Conventional analog-to-digital (A/D) converter designs utilizing tunneling diodes in high-performance processes (such as GaAs) have been designed based on performance characteristics peculiar to specific circuit components available in that process. Previous A/D converter designs suffer from a variety of performance limitations and, additionally, may not be readily adaptable to use in a CMOS process having tunneling structure capability.
To provide an illustration, a conventional A/D converter circuit 100 is shown in FIG. 1. Circuit 100 comprises four parallel processing assemblies, each representing a bit of the A/D code, divided by resistors 102, 104, and 106. A first assembly includes hetero-junction bipolar transistor (HBT) 108 coupled at its emitter to a series of four resonant tunneling diodes 110, the last of which couples to ground. The base of HBT 108 is coupled jointly to an input voltage V.sub.I and to a first end of resistor 102. A second end of resistor 102 couples to the base of HBT 112 which, in combination with a series of four resonant tunneling diodes 110 forms a second assembly, similar to the first. HBT 112 couples jointly at its base to a first end of resistor 104. Similarly, HBT 114 is intercoupled between resistors 104 and 106, and forms a third assembly with a series of four resonant tunneling diodes 110. Likewise, HBT 116 is intercoupled between resistors 106 and 118, and forms a fourth assembly with a series of four resonant tunneling diodes 110. Resistor 118 couples at its second end to ground, and has resistance value R.
The collector of HBT 108 couples jointly to a first end of load resistor 120 and a firstinput of comparator 122. A second end of load 120 couples to a supply voltage (V.sub.cc), while a second input of comparator 122 is coupled to a reference voltage (V.sub.REF). Comparator 122 outputs voltage V.sub.01. In similar fashion, HBT 112 is coupled to load 124 and comparator 126; with comparator 126 outputting voltage V.sub.02. Likewise, HBT 114 couple to load 128 and comparator 130, while HBT 116 couples to load 132 and comparator 134. Comparators 130 and 134 output voltages V.sub.03 and V.sub.04, respectively.
Resistor 102 has a value of 4R, resistor 104 a value of 2R, and resistors 106 and 118 values of R. The four parallel processing assemblies thus divide down V.sub.I, and thereby render a least significant bit (LSB) through most significant bit (MSB) for A/D conversion. Additionally, the use of TDs in such a design efficiently provides a folding characteristic, when compared with other, much more elaborate, conventional designs. In theory, the base of HBT 108 will have V.sub.I applied, the base of HBT 112 will have V.sub.I /2, the base of HBT 114 will have V.sub.I /4, and the base of HBT 116 will have V.sub.I /8.
However, conventional designs such as this suffer a variety of limitations. One such limitation is inherent in conventional architectures similar to circuit 100, and is illustrated in reference to FIG. 2. FIG. 2 represents a plot 200 of the output voltages V.sub.01 -V.sub.04 of circuit 100 with respect to input voltage V.sub.I. As V.sub.I increases, the four output voltages (representing the four bits of the converter) begin switching. By this design, when a maximum voltage is applied across HBT 108, for example, output V.sub.01 is low. Therefore, the digital information represented in FIG. 2 is a four bit inverted Gray-code representation of an input analog voltage V.sub.I. Further processing of the resultant digital signals is therefore necessary to render a desired positive digital code. This requires additional circuitry, such as inverting buffers at the output of each comparator; which increases power dissipation and layout area, and decreases speed and overall efficiency of the A/D device.
Other limitations of conventional designs are inherent in the use of HBTs. Each HBT has an inherent offset voltage due to its base-to-emitter voltage (V.sub.BE) . Thus the voltage processed at the first bit of circuit 100 is actually (V.sub.I -V.sub.BE), not V.sub.I. This level shift effect propagates down through each bit of the converter. The level shift has the effect of an offset in the reference voltage, causing errors. Additionally, if the V.sub.BE values of each bit aren't matched, non-linearity of the design will result. High speed HBTs have low beta values, which results in high base currents. Current leakage associated with those high base currents, as well as relatively large base currents required to operate the HBT at speed, can result reference voltage errors.
Conventional designs suffer from other design problems as well. Dynamic change of input impedances is characteristic of a design such as circuit 100, which can result in transient changes of bit voltages. Conventional designs required comparators to determine level changes for A/D functionality. Conventional comparators presented speed limitations; comparators capable of high speed operation presented size and power problems. Additionally, conventional designs lacked the ability to address the dynamic hysteresis of resonant tunneling diodes. This dynamic hysteresis introduced inconsistency into the A/D codes, which translated into non-linearity of the A/D device.
Therefore, high speed analog to digital conversion circuitry, incorporating quantum-mechanical tunneling structures, and readily usable in standard semiconductor processes (e.g. CMOS) as well as high-performance and hybrid processes (e.g. GaAs), is now needed; providing enhanced design performance and efficiency while overcoming the aforementioned limitations of conventional methods.